edi8f8512c 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. fig. 1 pin configurations features ? 512kx8 bit cmos static ? random access memory ? access times 20 through 100ns ? data retention function (edi8f8512lp) ? ttl compatible inputs and outputs ? fully static, no clocks ? high density packaging ? 36 pin sip, no. 63 ? 32 pin dip, jedec pinout, no. 91 (55-100ns) ? 32 pin dip, jedec pinout, no. 183 (20-35ns) ? single +5v (10%) supply operation *this product is subject to change without notice. the edi8f8512c is a 4096k bit cmos static ram based on four 128kx8 or 256kx4 (high speed) static rams mounted on a multi- layered epoxy laminate (fr4) substrate. functional equivalence to the monolithic four megabit static ram is achieved by utilization of an on-board decoder that interprets the higher order address(es) to select one of the128kx8 or 256kx4 static rams. the 32 pin dip pinout adheres to the jedec standard for the four megabit device, to ensure compatibility with future monolithics. a low power version with data retention (edi8f8512lp) is also available. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the edi8f8512c requires no clocks or refreshing for operation. 512kx8 static ram cmos, module description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 nc v cc w# dq2 dq3 dq0 a1 a2 a3 a4 v ss dq5 a10 a1 1 a5 a13 a14 nc e# a15 a16 a12 a18 a6 dq1 v ss a0 a7 a8 a9 dq7 dq4 dq6 a17 v cc g# 8f8512c pin config. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 8f8512c pin config 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc a15 a17 w# a13 a8 a9 a1 1 g# a10 e# dq7 dq6 dq5 dq4 dq3 pin names a0-a18 address inputs e# chip enable w# write enable g# output enable dq0-dq7 common data input/output v cc power (+5v10%) v ss ground nc no connection
edi8f8512c 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. dq0-7 128k x 8 128k x 8 128k x 8 128k x 8 a 0-16 w# g# a 17-a18 e# decoder 8f8512c blk dia fig. 2 block diagrams 55-100 ns dq 4-7 256k x 4 256k x 4 256k x 4 256k x 4 a 0-17 w# g# a18 e# decoder 8f8512c blk dia2 dq0-3 20-35 ns
edi8f8512c 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. absolute maximum ratings* recommended dc operating conditions ac test conditions *stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (note: for t ehqz , t ghqz and t wlqz , cl = 5pf) voltage on any pin relative to v ss -0.5v to 7.0v operating temperature t a (ambient) commercial industrial 0c to +70c -40c to +85c storage temperature -55c to +125c power dissipation 4 watt output current 20 ma input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 20-35ns 1ttl = 30pf 70-100ns 1ttl, cl = 100pf parameter sym min typ max units supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 0 0 0 v input high voltage v ih 2.2 C 6.0 v input low voltage v il -0.3 C 0.8 v dc electrical characteristics *typical: t a = 25c, v cc = 5.0v parameter sym conditions min typ* max units 35 55 20-25 35 55-100 operating power supply current i cc1 w#, e# = v il , ii/o = 0ma, min cycle 340 70 570 390 130 ma standby (ttl) power supply current i cc2 e# v ih , v in v il v in v ih dip sip C C 50 C 10 C 85 C 85 C 55 65 ma full standby power supply current (cmos) i cc3 e# v cc -0.2v v in v cc -0.2v or v in 0.2v c lp C C 5 C 2 40 40 C 40 C 5 400 ma a input leakage current i li v in = 0v to v cc C C C C 10 10 10 a output leakage current i lo v i/o = 0v to v cc C C C C 10 10 10 a output high voltage v oh i oh = -1.0ma ( 70), or -4.0 ( 35) 2.4 C C C C C C v output low voltage v ol i ol = 2.1ma ( 70), or 8.0ma ( 35) C C C C 0.4 0.4 0.4 v truth table capacitance (f=1.0mhz, v in =v cc or v ss ) these parameters are sampled, not 100% tested. g# e# w# mode output power x h x standby high z i cc2 /i cc3 h l h output deselect high z i cc1 l l h read d out i cc1 x l l write d in i cc1 parameter sym max unit address lines ci 30 pf data lines cd/q 43 pf chip enable line cc 10 pf write and output enable lines cw 32 pf
edi8f8512c 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. fig. 3 read cycle 1 - w# high, g#, e# low fig. 4 read cycle 2 - w# high address 1 address 2 t avav da ta 1 da ta 2 t av qv t av qx 8f8512c rd cyc1 a q t ghqz t elqv t elqx e# g# q t ehqz a t avav t glqv t glqx t av qv 8f8512c rd cyc2 ac characteristics read cycle parameter symbol 20ns 25ns 35ns units jedec alt. min. max. min. max. min. max. read cycle time t avav t rc 20 25 35 ns address access time t avqv t aa 20 25 35 ns chip enable access time t elqv t acs 20 25 35 ns chip enable to output in low z (1) t elqx t clz 3 3 3 ns chip disable to output in high z (1) t ehqz t chz 10 12 15 ns output hold from address change t avqx t oh 3 3 3 ns output enable to output valid t glqv t oe 13 15 20 ns output enable to output in low z (1) t glqx t olz 0 0 0 ns output disable to output in high z (1) t ghqz t ohz 8 10 12 ns note: parameter guaranteed, but not tested.
edi8f8512c 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics write cycle note 1: parameter guaranteed, but not tested. write cycle parameter symbol 20ns 25ns 35ns units jedec alt. min max min max min max write cycle time t avav t wc 20 25 35 ns chip enable to end of write t elwh t eleh t cw t cw 15 15 20 20 30 30 ns ns address setup time t avwl t avel t as t as 0 0 0 0 0 0 ns ns address valid to end of write t avwh t aveh t aw t aw 15 15 20 20 30 30 ns ns write pulse width t wlwh t wleh t wp t wp 15 15 20 20 25 25 ns ns write recovery time t whax t ehax t wr twr 0 0 0 0 0 0 ns ns data hold time t whdx t ehdx t dh t dh 3 3 3 3 3 3 ns ns write to output in high z (1) t wlqz t whz 0 10 0 12 0 15 ns data to write time t dvwh t dveh t dw t dw 12 12 15 15 20 20 ns ns output active from end of write (1) t whqx t wlz 3 3 3 ns ac characteristics read cycle note 1: parameter guaranteed, but not tested. symbol 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max units read cycle time t avav t rc 55 70 85 100 ns address access time t avqv t aa 55 70 85 100 ns chip enable access time t elqv t acs 55 70 85 100 ns chip enable to output in low z (1) t elqx t clz 5 5 5 5 ns chip disable to output in high z (1) t ehqz t chz 30 30 35 40 ns output hold from address change t avqx t oh 3 3 3 3 ns output enable to output valid t glqv t oe 40 40 45 50 ns output enable to output in low z (1) t glqx t olz 0 0 0 0 ns output disable to output in high z (1) t ghqz t ohz 30 30 35 40 ns
edi8f8512c 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. note 1: parameter guaranteed, but not tested. fig. 7 write cycle 1 - w# controlled e# a t avav t el wh t av wh t wl wh t av wl t whax w# high z da ta v alid t wlqz t whqx t dvwh t whdx q d 8f8512c w rite cyc1 ac characteristics write cycle parameter symbol 55ns 70ns 85ns 100ns units jedec alt. min max min max min max min max write cycle time t avav t wc 55 70 85 100 ns chip enable to end of write t elwh t eleh t cw t cw 50 50 65 65 70 70 80 80 ns ns address setup time t avwl t avel t as t as 0 0 0 0 0 0 0 0 ns ns address valid to end of write t avwh t aveh t aw t aw 50 50 65 65 70 70 80 80 ns ns write pulse width t wlwh t wleh t wp t wp 50 50 65 65 70 70 80 80 ns ns write recovery time t whax t ehax t wr t wr 0 0 0 0 0 0 0 0 ns ns data hold time t whdx t ehdx t dh t dh 0 0 0 0 0 0 0 0 ns ns write to output in high z (1) t wlqz t whz 0 30 0 30 0 35 0 40 ns data to write time t dvwh t dveh t dw t dw 30 30 30 30 35 35 40 40 ns ns output active from end of write (1) t whqx t wlz 5 5 3 5 ns
edi8f8512c 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. fig. 8 write cycle 2 - e# controlled a t av el high z t avav 8f8512c w rite cyc2 t eleh e# t av eh t ehax w# t wleh t ehdx t dveh q da ta v alid d
edi8f8512c 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. lp 70-100ns only ordering information standard power speed (ns) package no. edi8f8512c20m6c 20 183 edi8f8512c25m6c 25 183 edi8f8512c35m6c 35 183 edi8f8512c70bsc 70 63 edi8f8512c85bsc 85 63 edi8f8512c100bsc 100 63 edi8f8512c55b6c 55 91 edi8f8512c70b6c 70 91 edi8f8512c85b6c 85 91 edi8f8512c100b6c 100 91 low power with data retention speed (ns) package leads edi8f8512lp70bsc 70 63 edi8f8512lp85bsc 85 63 edi8f8512lp100bsc 100 63 edi8f8512lp70b6c 70 91 edi8f8512lp85b6c 85 91 EDI8F8512LP100B6C 100 91 note: to order an industrial grade product substitute the letter c in the suf?x with the letter i, e.g., edi8f8512c70b6c becomes edi8f8512c70b6i. fig. 9 data retention e# controlled v cc t r 8f8512c data retent . d ata retention mode e# t cdr e# v cc -0.2v v cc 4.5v 4.5v data retention characteristics *read cycle time note: parameter guaranteed, but not tested. characteristic sym test conditions v cc min typ max unit 70c 85c data retention voltage v cc v cc = 0.2v 2 C C C v data retention quiescent current i ccdr e# v cc -0.2v v in v cc -0.2v or v in 0.2v 2v C 10 125 185 a 3v C 20 200 250 a chip disable to data retention time (1) t cdr 0 C C C ns operation recovery time (1) t r t avav * C C C ns
edi8f8512c 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs july 2002 rev. 13a white electronic designs corp. reserves the right to change products or speci? cations without notice. package no. 63: 36 pin single-in-line package package descriptions 8f8512c pkg 2 1.665 max. .085 .065 .175 .125 .025 .015 .620 .590 .248 max. .640 max. note 2 u5 u1 u2 r1 r2 .100 typ . 15 x .100 1.500 ref . 0.125 mi n 4.040 max. 0.020 0.016 0.575 0.565 0.150 ma x 0.100 35 x 0.100 = 3.500 8f8512c pkg1 all dimensions are in inches 8f8512c pkg3 .010 .005 1.715 max. .640 max. .355 max. 1 .175 .125 .620 .590 15 x .100 1.500 ref . not recommended for new designs package no. 91: 32 pin dual-in-line package package no. 183: 32 pin dual-in-line package
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